[Mono-dev] ir instructions.

[Rodrigo Kumpera]

On Sat, Feb 20, 2010 at 2:07 AM, Jerry Maine - KF5ADY <crashfourit at gmail.com
> wrote:

> Rodrigo:
>
> I remember you talking about instead of having marcos and defines
> describe certain attributes of IR instructions, having them be defined
> in a single data structure like what is done for when calling LLVM. What
> would that entail?
>

That would entail been able to encode more properties and relations of
instructions
without all the repetition that currently exist in our JIT.

I am getting more interested in that project as a was thinking it would
> be quite a bit helpful in the other projects I'd like to do, and may be
> even needed in some parts.
>

I talked abou that with Paolo and he suggested that this it would be better
done without
using a tool like llvm's tablegen. Thou we didn't talk much further, so I'm
CC'ing him so
he can give us a better idea of what he has on his mind.

There are 3 different problems I think deserve been solved.

The first is encoding of instruction properties such as commutative or
side-effect free.
For this it would be a matter of adding an extra parameter to the MINI_OP
macro or'ing
those properties and then filling a table with this data.

The second is encode relations between instructions. For example,
op_to_op_dest_membase
is only enabled on x86/amd64 and to small amount of operations. Doing this
for all SIMD ops
would be a a lot of repetitive work.

The last is to reduce the amount of repetition between instructions
definitions, it has to be very
template oriented and support customization of the result. For example, I
want to define a single
template for binary SIMD ops that produce reg_reg, reg_membase, reg_memindex
variants, which
don't have side effects and, finally, can be easily instantiated for the
many vector elements.

This is asking for a lot. But it would simplify the JIT a lot and make it
produce better code easier.

Rodrigo
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