[Mono-dev] Building Mono on Linux/Alpha

[Sergey Tikhonov]

Massimiliano Mantione wrote:

>On Thu, 2006-09-07 at 12:29 -0400, Miguel de Icaza wrote:
>  
>
>>Hello,
>>
>>    
>>
>>>I have some questions about mono_local_regalloc. Is it possible to tell 
>>>its logic right now not to reuse the same
>>>physical register in the same instruction? Alpha has "a lot" of 
>>>registers and experience some penalty if the same
>>>register is used in the same or next instruction when results of 
>>>previous instruction are not needed for next. For example:
>>>      
>>>
>>This is a design consideration that might be worth including in the next
>>register allocator.
>>    
>>
>
>Interesting...
>
>This also looks relatively easy to do, I will take it into account.
>I say "relatively easy" because the new regalloc, unlike the previous
>one,
>is able (and willing) to split liveness ranges at each definition, so
>that
>in practice each definition of the same vreg could go into a different
>hard register if necessary (of course if this does not introduce too
>many
>useless "resolution" moves at BB boundaries).
>
>Just to be sure I got it right: when there is more than one free
>register
>to choose from, all else being equal, the regalloc should favor
>registers
>that have been freed earlier instead of later.
>Handling free registers like a FIFO queue during the linear allocation
>should be enough to do this trick: at BB boundaries the heuristic could
>fail, but elsewhere it should do exactly what Sergey asked.
>Of course, if a special/particular register is needed, the regalloc can
>walk the queue and pick what it needs, this is just to get you the idea.
>
>Comments?
>  
>
Well, after reading specs for alpha,x86/amd64,ia64 cpus. I see that that 
only issue that could be avoided by
using new register is WAW (write-after-write) problem. Current code 
pattern has a lot of instructions like this:
load from memory to temp reg
save temp reg to memory
load from memory to temp reg
save temp reg to memory
The second load/save could not be issued at the same time (by current 
out of order cpus), because it has to use
the same temp register as the first load/store. I think your solution 
should work.
Is there place in current design where instruction scheduling at IR 
level could be implemented? (before local regalloc assignment)
Just wandering. :)

Regards,

-- 
Sergey Tikhonov

Solvo Ltd.
Saint-Petersburg, Russia
tsv at solvo.ru