[Mono-dev] Global register allocator in JIT

[Sergey Tikhonov]

Hello,

Here is another example I am trying to understand:
The IL code is:
converting (in B8: stack: 0) IL_0025: ldarg.0
converting (in B8: stack: 1) IL_0026: conv.i
converting (in B8: stack: 1) IL_0027: ldc.i4.0
converting (in B8: stack: 2) IL_0028: add
converting (in B8: stack: 1) IL_0029: ldarg.1
converting (in B8: stack: 2) IL_002a: conv.i
converting (in B8: stack: 2) IL_002b: ldc.i4.0
converting (in B8: stack: 3) IL_002c: add
converting (in B8: stack: 2) IL_002d: ldind.u1
converting (in B8: stack: 2) IL_002e: stind.i1
converting (in B8: stack: 0) IL_002f: ldarg.0
converting (in B8: stack: 1) IL_0030: ldc.i4.1
converting (in B8: stack: 2) IL_0031: add
converting (in B8: stack: 1) IL_0032: starg.s   0
converting (in B8: stack: 0) IL_0034: ldarg.1
converting (in B8: stack: 1) IL_0035: ldc.i4.1
converting (in B8: stack: 2) IL_0036: add
converting (in B8: stack: 1) IL_0037: starg.s   1
converting (in B8: stack: 0) IL_0039: ldarg.2
converting (in B8: stack: 1) IL_003a: ldc.i4.1
converting (in B8: stack: 2) IL_003b: sub
converting (in B8: stack: 1) IL_003c: starg.s   2

Converted to:
DUMP BLOCK 8:
 (stind.i1 (long_add (long_conv_to_i (ldind.i regvar[alpha_r12])) 
iconst[0]) (ldind.u1 (long_add (long_conv_to_i (ldind.i 
regvar[alpha_r13])) iconst[0])))
 (stind.i regvar[alpha_r12] (long_add (ldind.i regvar[alpha_r12]) 
iconst[1]))
 (stind.i regvar[alpha_r13] (long_add (ldind.i regvar[alpha_r13]) 
iconst[1]))
 (stind.i4 regvar[alpha_r14] (sub (ldind.i4 regvar[alpha_r14]) iconst[1]))

The second and third line uses r12 and r13 registers (as wished).

LOCAL REGALLOC: BASIC BLOCK: 8
        1  move R31 <- alpha_r12
        2  move R34 <- alpha_r13
        3  loadu1_membase R33 <- R34
        4  storei1_membase_reg [R31] <- R33
        5  add_imm R36 <- alpha_r12
        6  move alpha_r12 <- R36
        7  add_imm R38 <- alpha_r13
        8  move alpha_r13 <- R38
        9  int_sub_imm R40 <- alpha_r14
        10 move alpha_r14 <- R40

The better code would be:
LOCAL REGALLOC: BASIC BLOCK: 8
        3  loadu1_membase R33 <- alpha_r13
        4  storei1_membase_reg [alpha_r12] <- R33
        5  add_imm alpha_r12 <- alpha_r12
        7  add_imm alpha_r13<- alpha_r13
        9  int_sub_imm alpha_r14 <- alpha_r14

I tried to defined the following brg rules, but it failed. What did I do 
wrong? :(
stmt: CEE_STIND_I (OP_REGVAR, CEE_ADD (reg, OP_ICONST)) {
        MONO_EMIT_BIALU_IMM (s, tree, OP_ADD_IMM, state->left->tree->dreg,
                state->right->left->reg1, 
state->right->right->tree->inst_c0);
}
stmt: CEE_STIND_I (OP_REGVAR, CEE_ADD (OP_REGVAR, OP_ICONST)) {
        MONO_EMIT_BIALU_IMM (s, tree, OP_ADD_IMM, state->left->tree->dreg,
                state->right->left->reg1, 
state->right->right->tree->inst_c0);
}

I am afraid that adding more global regs (for now I am just using only 
3) would make the code longer and
slower. :(

Thank you,
Sergey.

tsv at solvo.ru
Solvo Ltd.