[Mono-bugs] [Bug 61641][Wis] Changed - Bad register allocation with `if' statements

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Changed by bmaurer@users.sf.net.

http://bugzilla.ximian.com/show_bug.cgi?id=61641

--- shadow/61641	2004-07-15 20:40:47.000000000 -0400
+++ shadow/61641.tmp.25615	2004-07-15 22:12:20.000000000 -0400
@@ -588,6 +588,15 @@
 
 I think the second arrangement would give better allocation.
 
 ------- Additional Comments From bmaurer@users.sf.net  2004-07-15 20:40 -------
 So obviously you cant really do the preorder visit correctly if the
 graph has cycles.
+
+------- Additional Comments From bmaurer@users.sf.net  2004-07-15 22:12 -------
+in
+http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/cfganal.c?rev=1.45&content-type=text/x-cvsweb-markup
+
+flow_depth_first_order_compute
+
+The `rc' (reverse completion) order seems like what we want. I need to
+look at this more.