[Mono-bugs] [Bug 29000][Min] Changed - Incorrect right-evaluation in assignament

bugzilla-daemon@rocky.ximian.com bugzilla-daemon@rocky.ximian.com
16 Aug 2002 08:55:02 -0000


Please do not reply to this email- if you want to comment on the bug, go to the
URL shown below and enter your comments there.

Changed by dietmar@ximian.com.

http://bugzilla.ximian.com/show_bug.cgi?id=29000

--- shadow/29000	Thu Aug 15 06:08:39 2002
+++ shadow/29000.tmp.27897	Fri Aug 16 04:55:02 2002
@@ -1,16 +1,16 @@
 Bug#: 29000
-Product: Mono/Runtime
+Product: Mono/MCS
 Version: unspecified
 OS: Debian Woody
 OS Details: 
 Status: NEW   
 Resolution: 
-Severity: 
+Severity: Unknown
 Priority: Minor
-Component: misc
+Component: Misc
 AssignedTo: mono-bugs@ximian.com                            
 ReportedBy: sergio.gomez@consejo-eps.uco.es               
 QAContact: mono-bugs@ximian.com
 TargetMilestone: ---
 URL: 
 Cc: 
@@ -60,6 +60,49 @@
 Always
 
 Additional Information:
 
 bash$ dpkg -s mono |grep Version
 Version: 0.13-20020813-1
+
+------- Additional Comments From dietmar@ximian.com  2002-08-16 04:55 -------
+Both csc and mcs generates incorrect IL code! Below is example with a
+= 1100; b = 0110; (binary values) to show whats going on:
+
+csc code sequesnce:
+
+	IL_0022: ldloc.0  1100
+	IL_0023: ldloc.1  1100 0110
+	IL_0024: ldloc.0  1100 0110 1100
+	IL_0025: ldloc.1  1100 0110 1100 0110 
+	IL_0026: xor      1100 0110 1010
+	IL_0027: dup      1100 0110 1010 1010
+	IL_0028: stloc.0  1100 0110 1010          V0 = 1010
+	IL_0029: xor      1100 1100
+	IL_002a: dup      1100 1100 1100
+	IL_002b: stloc.1  1100 1100               V1 = 1100
+	IL_002c: xor      0000 
+	IL_002d: stloc.0                          V0 = 0000
+
+
+mcs code sequence:
+
+	IL_0022: ldloc.0  1100
+	IL_0023: ldloc.1  1100 0110
+	IL_0024: ldloc.0  1100 0110 1100
+	IL_0025: ldloc.1  1100 0110 1100 0110 
+	IL_0026: xor      1100 0110 1010
+	IL_0027: stloc.3  1100 0110               V3 = 1010
+	IL_0028: ldloc.3  1100 0110 1010
+	IL_0029: stloc.0  1100 0110               V0 = 1010
+	IL_002a: ldloc.3  1100 0110 1010
+	IL_002b: xor      1100 1100 
+	IL_002c: stloc.2  1100                    V2 = 1100
+	IL_002d: ldloc.2  1100 1100
+	IL_002e: stloc.1  1100                    V1 = 1100
+	IL_002f: ldloc.2  1100 1100
+	IL_0030: xor      0000
+	IL_0031: stloc.0                          V0 = 0000
+
+mcs generates the same wrong code as csc, but it add some additional 
+load/stores.
+